24-06-2013, 04:28 PM
You need to divide by 2^17 or 2^18. Principle problem is the initial frequency of 186MHz - dividing that is beyond CMOS and 74HC(T) logic - you need a specialised prescaler.
A prescaler, such as a Motorola MC12013 (/10) or NXP SAB6456T (/64 or /256), followed by a divide-by-n counter 74HCT4059 would do that... note that at these frequencies constructional technique becomes critical (certainly for the prescaler) - a "Manhattan" technique would do the job...
The following circuit will take your divided pulse train and use that to fire a 555 wired as a monostable producing about 700uS pulses which get integrated by the 10uF (not 10pF as on the schematic) capacitor across the analogue meter (1mA FSD).
At 1kHz the pulses almost, but not entirely, join up which gives you the max frequency that this integrator will handle...
The reason you need the monostable is that your divided down 186MHz will have a 50:50 duty cycle, so its RMS value will be 50% of peak regardless of frequency, so you can't feed the divided down signal directly into an integrator.
However, the real problem is you only want a scale from 60MHz to 186MHz and you have an IF offset of 21MHz to remove as well. I have to say, this is classic micro-processor territory... it would be pretty trivial to do almost all this with a PIC or AVR processor for peanuts...
A prescaler, such as a Motorola MC12013 (/10) or NXP SAB6456T (/64 or /256), followed by a divide-by-n counter 74HCT4059 would do that... note that at these frequencies constructional technique becomes critical (certainly for the prescaler) - a "Manhattan" technique would do the job...
The following circuit will take your divided pulse train and use that to fire a 555 wired as a monostable producing about 700uS pulses which get integrated by the 10uF (not 10pF as on the schematic) capacitor across the analogue meter (1mA FSD).
At 1kHz the pulses almost, but not entirely, join up which gives you the max frequency that this integrator will handle...
The reason you need the monostable is that your divided down 186MHz will have a 50:50 duty cycle, so its RMS value will be 50% of peak regardless of frequency, so you can't feed the divided down signal directly into an integrator.
However, the real problem is you only want a scale from 60MHz to 186MHz and you have an IF offset of 21MHz to remove as well. I have to say, this is classic micro-processor territory... it would be pretty trivial to do almost all this with a PIC or AVR processor for peanuts...
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