26-04-2024, 06:58 PM
(This post was last modified: 26-04-2024, 07:17 PM by Mike Watterson.)
It looks to me like the A & V modes and offsets are all separate.
Also it looks like the chip doesn't use intercarrier as such, like the simple VHS modulators with brass screw and 6MHz FM Osc fed in parallel with video.
Section 9 and 10 onwards:
Sound offset
SFD1 & SFD0
00 4.5
01 5.5
10 6.0
11 6.5
N0-N11: Divider to set RF. At other than 4MHz ref, the limits may be exceeded
These are obviously read, not written
Table 19
OOR: 1= Out of Range. 0 = locked.
Y1: Out of range low or high if OOR = 1
Y2: High or low VCO (this needs explained)
Video set
SYSL =0 FM sound & negative video
SYSL =1 AM sound & positive video
PWC = 1 for peak white clip (normally only for FM sound & neg video mod)
TPEN =1 (Test pattern & tone). 0 for normal.
Other PLL sound modulator reference (loop filter caps ext)
SREF 0 = 31.25 kHz (Really ext 4 MHz / 256)
SREF 0 = 62.5 kHz (Really ext 4 MHz / 128)
X bits= Test Mode/VHF
000 Normal (about 460 MHz to 880 MHz)
001 RF/2
010 RF/4
011 RF/8
100 RF/16
101 UHF only non-inverted video. DC drive
110 UHF only inverted video. DC drive
111 Transient inhibit disabled. UHF only.
Bits X3, X4 and X5 should be all 0, others are test modes.
So only values 0 to 4 for X0 to X5 bits.
The internal UHF oscillator (or maybe two of them) will be 460 MHz to 880 MHz, no matter what the external 4 MHz really is or what N0 to N11 is set. The N0 to N11 is a divide by N from the VCO to a comparator. The external reference Ce (4MHz default) is divided by 128.
Thus UHF = N x Ce/128, but must be between 460 and 880 (the VCO range).
The VCO is then either direct to video modulator or via /2, /4 /8 or /16 (which will also divide the "steps")
The steps for each change of 1 on N is Ce/(128 *(X0 to X2 prescale)
It's not clear, but it looks like the VCO direct or divided by 2, 4, 8 or 16 goes to a second modulator so that the sound subcarrier is mixed up. It could be using several multipliers so as to only have Fv + Fssc components. This lets System L work (AM sound & positive video) instead of just adding the Sound sub-carrier to the video like on BGI systems.
The block diagram for sound part of the chip is also a PLL synth but using either Fext /128 or /64 as it has a separate PLL LPF. However a 4.5MHz to 6.5 MHz VCO with no external varicap seems strange, so suspect it's a higher frequency divided down.
It may be that the onboard audio offset LO can't go much below 4.5 MHz. Or it may be that the block diagram is totally misleading.
Actually there is a /8 btween VCO and /N, so steps are 8x Fxet/128
A spectrum analyser and an external signal generator instead of the 4 MHz crystal would reveal a lot.
Also it looks like the chip doesn't use intercarrier as such, like the simple VHS modulators with brass screw and 6MHz FM Osc fed in parallel with video.
Section 9 and 10 onwards:
Sound offset
SFD1 & SFD0
00 4.5
01 5.5
10 6.0
11 6.5
N0-N11: Divider to set RF. At other than 4MHz ref, the limits may be exceeded
These are obviously read, not written
Table 19
OOR: 1= Out of Range. 0 = locked.
Y1: Out of range low or high if OOR = 1
Y2: High or low VCO (this needs explained)
Video set
SYSL =0 FM sound & negative video
SYSL =1 AM sound & positive video
PWC = 1 for peak white clip (normally only for FM sound & neg video mod)
TPEN =1 (Test pattern & tone). 0 for normal.
Other PLL sound modulator reference (loop filter caps ext)
SREF 0 = 31.25 kHz (Really ext 4 MHz / 256)
SREF 0 = 62.5 kHz (Really ext 4 MHz / 128)
X bits= Test Mode/VHF
000 Normal (about 460 MHz to 880 MHz)
001 RF/2
010 RF/4
011 RF/8
100 RF/16
101 UHF only non-inverted video. DC drive
110 UHF only inverted video. DC drive
111 Transient inhibit disabled. UHF only.
Bits X3, X4 and X5 should be all 0, others are test modes.
So only values 0 to 4 for X0 to X5 bits.
The internal UHF oscillator (or maybe two of them) will be 460 MHz to 880 MHz, no matter what the external 4 MHz really is or what N0 to N11 is set. The N0 to N11 is a divide by N from the VCO to a comparator. The external reference Ce (4MHz default) is divided by 128.
Thus UHF = N x Ce/128, but must be between 460 and 880 (the VCO range).
The VCO is then either direct to video modulator or via /2, /4 /8 or /16 (which will also divide the "steps")
The steps for each change of 1 on N is Ce/(128 *(X0 to X2 prescale)
It's not clear, but it looks like the VCO direct or divided by 2, 4, 8 or 16 goes to a second modulator so that the sound subcarrier is mixed up. It could be using several multipliers so as to only have Fv + Fssc components. This lets System L work (AM sound & positive video) instead of just adding the Sound sub-carrier to the video like on BGI systems.
The block diagram for sound part of the chip is also a PLL synth but using either Fext /128 or /64 as it has a separate PLL LPF. However a 4.5MHz to 6.5 MHz VCO with no external varicap seems strange, so suspect it's a higher frequency divided down.
It may be that the onboard audio offset LO can't go much below 4.5 MHz. Or it may be that the block diagram is totally misleading.
Actually there is a /8 btween VCO and /N, so steps are 8x Fxet/128
A spectrum analyser and an external signal generator instead of the 4 MHz crystal would reveal a lot.
