26-04-2024, 11:55 AM
(This post was last modified: 26-04-2024, 12:07 PM by Mike Watterson.)
Actually the minimum UHF oscillator is 460 MHz rather than 471 MHz suggested by C21.
15.7 UHF PLL Section
The reference divider is a fixed divide-by-128, resulting in a reference frequency of 31.25 kHz with a
4.0-MHz crystal.
The prescaler is a fixed divide-by-8 and is permanently engaged.
The programmable divider division ratio is controlled by the state of control bits N0 to N11.
The divider ratio N for a desired frequency F (in MHz) is given by:
F 128
N = --- × ----------
8
4
with:
N = 2048 × N11 + 1024 × N10 + ...... + 4 × N2 + 4 × N1 + N0
(I think that should be 2 x N1)
Obviously minimum is 2048 x1
If other than 4MHz reference is used the 2048 is the reference / 2, thus for 3.111111 MHz the equation is
N MHz = 1555.555555 × N11 + 777.777 × N10 + ...... etc, or original x ratio of (new clock)/4
However the minimum frequency for lock may still be near 460 MHz, so the minimum N0 to N11 is more than 1.
15.7 UHF PLL Section
The reference divider is a fixed divide-by-128, resulting in a reference frequency of 31.25 kHz with a
4.0-MHz crystal.
The prescaler is a fixed divide-by-8 and is permanently engaged.
The programmable divider division ratio is controlled by the state of control bits N0 to N11.
The divider ratio N for a desired frequency F (in MHz) is given by:
F 128
N = --- × ----------
8
4
with:
N = 2048 × N11 + 1024 × N10 + ...... + 4 × N2 + 4 × N1 + N0
(I think that should be 2 x N1)
Obviously minimum is 2048 x1
If other than 4MHz reference is used the 2048 is the reference / 2, thus for 3.111111 MHz the equation is
N MHz = 1555.555555 × N11 + 777.777 × N10 + ...... etc, or original x ratio of (new clock)/4
However the minimum frequency for lock may still be near 460 MHz, so the minimum N0 to N11 is more than 1.







