Hedghog Mk II

[ppppenguin]

AL422B data: http://www.averlogic.com/AL422B.asp

It's available from RS which suggests it's still current: https://uk.rs-online.com/web/p/fifo-memo...s/7496657/

It was used in the Domino converter.

[Terry]

I think Terry proposed the idea of a SAW filter in another thread ...

I did indeed! Here it is: https://golbornevintageradio.co.uk/forum...p?tid=6791&pid=74187#pid74187

[`FRANK.C]

Thinking about what Jeffrey was saying in post #5.
It should be possible to build a standards converter where the output standard is user defined. With the user just needing to enter the parameters such as number lines, length of front porch, length of sync pulse. number of broad pulses etc.
It would need a frame store. A microcontroller and LCD could easily take care of the user interface and also provide storage for the imputed parameters.

I cant think of any big obstacle. Not having a way of viewing the non 405 standards might be a problem as it would be difficult to know how well the interpolater coefficients were preforming when not producing 405.

It may not be easy and would need a lot of work but it looks doable.

Frank

[ppppenguin]

It would be possible to have variable output standard. A microcontroller would be very useful though you could do it without one if you tried hard. Best to use a framstore. Then you can always have the interpolator after the memory. With a linestore design the interp must be ahaed of the time redistributor if lines out < lines in. Such as 625 to 405. If other way round then interp must be after redistributor. Such as 625>819.

The interpolator function for 405 will be OK over a pretty wide range of output standards. Below 250 and above 625 you might want different sets of coeffts.

[ppppenguin]

Darryl's WC-01 converter (only a few ever made) was switchable to just about every known standard. From what I remember it used a bigger FPGA (Xilinx XC3S600 rings a bell) , SDRAM for framestore, a microcontroller and the same modulator chips as the SCRF and Hedghog. Mine is out on long term loan to somebody who needs the 240 line capability so I can't just open it up to look.

[Jac Janssen]

Jeffrey, you memory is quite accurate!

According to the manual the FPGA is a Xilinx XC3S500E-5PQ208 and the SDRAM Micron MT48LC8M16A2-7E 8M x 16 SDRAM.
(Unfortunately I don't have a WC-01 converter. I should have bought one when the dollar was very low...)
A 240 line converter would be very welcome here.

Jac

[ppppenguin]

I'm thinking about the best way to do 240/25p. I think I'd just use one of the input fields and interpolate from that. With a framestore it's no problem to write at 50Hz while reading at 25Hz. It wouldn't be worth interpolating from both fields as that would imply de-interlacing. That would look horrible on any movement unless done with pretty advanced processing.

There would be no technical problems doing this on my experimental converter but it's not something I want to work on at the moment. If I decide to do it, I don't have a 240/25p set. I'd probably borrow Paul Marshall's modified monitor that he used to demonstrate 240p against 405i some years ago.

[`FRANK.C]

Hi Jeffrey
I hadn't thought of it in that ways. That's makes it easier to do only one AL422 required even though I had a second AL422 on board ready to do the de-interlacing .

Frank

[ppppenguin]

As I've said before, don't bother with de-interlacing. With simple methods it will look utterly horrible on moving images.

[peter scott]

What is happening here?

   

My first thought here is that the Sony on the right has a line linearity problem but in the video the Hedghog is switched to the test card and the effect doesn't appear to confirm that???

https://youtu.be/aq9NPuezrQk

Peter