18-11-2018, 10:24 AM
(This post was last modified: 18-11-2018, 10:25 AM by ppppenguin.)
Yet more thoughts.
When you do the sums for utilising the DAC's range you want to be 100% certain that the sum total of sound and vision carriers can never wrap around from FSD to zero or vice versa. one way of doing this is to scale everything down a bit, maybe 10%. Another is to calculate with more bits than needed and do a limiter.
For example if the input is 16 bit signed and you want a 14 bit slv or unsigned output.
if myinput > conv_std_logic_vector(16383, 16) then myoutput <= conv_std_logic_vector(16383, 14);
elsif myinput < conv_std_logic_vector(0, 16) then myoutput <= conv_std_logic_vector(0, 14);
else myoutput <= myinput(13 downto 0); -- I think you can do this without casting signed to unsigned or slv. Otherwise it's: else myoutput <= unsigned( myinput(13 downto 0));
end if;
When you do the sums for utilising the DAC's range you want to be 100% certain that the sum total of sound and vision carriers can never wrap around from FSD to zero or vice versa. one way of doing this is to scale everything down a bit, maybe 10%. Another is to calculate with more bits than needed and do a limiter.
For example if the input is 16 bit signed and you want a 14 bit slv or unsigned output.
if myinput > conv_std_logic_vector(16383, 16) then myoutput <= conv_std_logic_vector(16383, 14);
elsif myinput < conv_std_logic_vector(0, 16) then myoutput <= conv_std_logic_vector(0, 14);
else myoutput <= myinput(13 downto 0); -- I think you can do this without casting signed to unsigned or slv. Otherwise it's: else myoutput <= unsigned( myinput(13 downto 0));
end if;
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv