29-10-2018, 10:28 AM
I thought I would share this as it might help others.
I was sent a newly constructed Hedghog that was producing a very bad picture. The photo below is of the test card that it produced.
The test card shown is through an external modulator. Through its own modulator the picture was far worse. Its fairly clear from the test card that the pixel clock is all over the place. The fact that through its own modulator was worse would suggest that the 4 MHz clock feeding the modulators was effected as well. The I2c clock is generated by dividing down the 50 MHz oscillator which is on the FPGA board. All other clocks are derived from the 27 MHz data clock produced by the TVP5150 video decoder. The 405 line pixel clock and the 4 MHz modulator clock are produced from a PLL within the FPGA. The cause of the problem could well be a faulty FPGA or something wrong with the 27 MHz clock. The simplest check to do was to plug in a known good FPGA board and this made no improvement. So out with the scope and I checked the 27 MHz clock(pin 9 of the TVP5150) the results can be seen in the photo below.
It was very unstable and clearly the cause of the problem. A check on the 14.31818 MHz crystal (pin 6 of the TVP5150) showed it was producing a nice clean sine wave. So the problem must be within the PLL section of the TVP5150. There are no external components associated with the TVP5150's PLL. There are just two pins 3 and 4 which are for the PLL's GND and VDD connections. Both of these were OK. The VDD supply to the PLL was correct and clean as was all the supplies to the TVP5150. The only thing left was the TVP5150 itself. Changing this cured the problem.
I have uploaded a pdf of some oscillographs of waveforms taken at different points.They might be of help if troubleshooting Hedghog. They were all taken using a X1 probe. There are better and more accurate ways at looking at waveforms but for trouble shooting I believe a X1 probe is good enough and it is what most would have to hand.
Frank
I was sent a newly constructed Hedghog that was producing a very bad picture. The photo below is of the test card that it produced.
The test card shown is through an external modulator. Through its own modulator the picture was far worse. Its fairly clear from the test card that the pixel clock is all over the place. The fact that through its own modulator was worse would suggest that the 4 MHz clock feeding the modulators was effected as well. The I2c clock is generated by dividing down the 50 MHz oscillator which is on the FPGA board. All other clocks are derived from the 27 MHz data clock produced by the TVP5150 video decoder. The 405 line pixel clock and the 4 MHz modulator clock are produced from a PLL within the FPGA. The cause of the problem could well be a faulty FPGA or something wrong with the 27 MHz clock. The simplest check to do was to plug in a known good FPGA board and this made no improvement. So out with the scope and I checked the 27 MHz clock(pin 9 of the TVP5150) the results can be seen in the photo below.
It was very unstable and clearly the cause of the problem. A check on the 14.31818 MHz crystal (pin 6 of the TVP5150) showed it was producing a nice clean sine wave. So the problem must be within the PLL section of the TVP5150. There are no external components associated with the TVP5150's PLL. There are just two pins 3 and 4 which are for the PLL's GND and VDD connections. Both of these were OK. The VDD supply to the PLL was correct and clean as was all the supplies to the TVP5150. The only thing left was the TVP5150 itself. Changing this cured the problem.
I have uploaded a pdf of some oscillographs of waveforms taken at different points.They might be of help if troubleshooting Hedghog. They were all taken using a X1 probe. There are better and more accurate ways at looking at waveforms but for trouble shooting I believe a X1 probe is good enough and it is what most would have to hand.
Frank