19-03-2018, 02:30 PM

It's a while since I designed my 161 tap monster. It was for upsampling a 13.5MHz signal to 54MHz with wide bandwidth and very flat response. The final design was flat within 0.018dB to 5.75MHz with 60dB stopband attenuation. Possibly overkill but it was feasible in the Xilinx I was using. I used an online Parks McClellan/Remez tool that's no longer available. Due to symmetry and 4x oversampling each multiplier served 8 taps. Plus an extra mutliplier for the central tap.

It's very much a guess but I think a 17 tap filter needing 3 mutlipliers would give good enough results for many purposes. Going down to 9 taps and 2 multipliers might not be too bad. If you push the passband too close to half the input sampling frequency that really ups the number of taps. As does flattening the passband response. 0.02dB flatness needs many more taps than 0.2dB. For our kind of 615 to 405 converter a passband flatness of 1dB would be entirely adequate. If you wanted the equivalent of 3.5MHz BW at 405 lines that would equate to 3.5*625/405=5.4MHz at 625. It may not sound very different, but it's a much simpler proposition than 5.75MHz. It's the difference between 80% and 85% of the Nyquist limit.

I don't know what sort of oversampling filter Darryl used at the output of the Aurora. It's clearly good enough and there are only 4 multipliers in a Xilinx 3S100E. One of them must have been used in the vertical interpolator so a maximum of 3 for the oversampler.

Note: The Aurora uses 3 line vertical interpolation which requires 3 mutliplies per pixel. Provided the internal clock is at least 3x faster than the pixel rate this can be done in a single multiplier. In my own experimental converter I allowed for up to 4 line interpolation and ran the mutliplier at 4x pixel frequency. This was critical in my design as it used a (now) very old Spartan 2 Xilinx which doesn't have hardware mutlipliers. So they have to be built out of ordinary logic. The Xilinx tools do a good job but it's still resource hungry.

It's very much a guess but I think a 17 tap filter needing 3 mutlipliers would give good enough results for many purposes. Going down to 9 taps and 2 multipliers might not be too bad. If you push the passband too close to half the input sampling frequency that really ups the number of taps. As does flattening the passband response. 0.02dB flatness needs many more taps than 0.2dB. For our kind of 615 to 405 converter a passband flatness of 1dB would be entirely adequate. If you wanted the equivalent of 3.5MHz BW at 405 lines that would equate to 3.5*625/405=5.4MHz at 625. It may not sound very different, but it's a much simpler proposition than 5.75MHz. It's the difference between 80% and 85% of the Nyquist limit.

I don't know what sort of oversampling filter Darryl used at the output of the Aurora. It's clearly good enough and there are only 4 multipliers in a Xilinx 3S100E. One of them must have been used in the vertical interpolator so a maximum of 3 for the oversampler.

Note: The Aurora uses 3 line vertical interpolation which requires 3 mutliplies per pixel. Provided the internal clock is at least 3x faster than the pixel rate this can be done in a single multiplier. In my own experimental converter I allowed for up to 4 line interpolation and ran the mutliplier at 4x pixel frequency. This was critical in my design as it used a (now) very old Spartan 2 Xilinx which doesn't have hardware mutlipliers. So they have to be built out of ordinary logic. The Xilinx tools do a good job but it's still resource hungry.

Jeffrey Borinsky http://www.borinsky.co.uk