09-02-2018, 08:44 PM
Hi Jeffrey
It will be a right pain if you have to learn Verilog but I guess needs must. I think Varilog is similar to C.
I wonder what those converters are like, would you end up with the equivalent of a modern user manual, the gist of it being there but it not being quite right.
I am glad that I decided to go with VHDL instead of Verilog, as I get know VHLD the more I like it, it's a really nice language to use.
When I started I was getting mixed up particularly between SLV's and integer's, so I started again from scratch this time using solely std_logic and SLV's. Writing in this way is long winded but it saved an untold amount of errors. When I got a better feel for the language I introduced integer's which made the files much easier to read. I still haven't used boolean but the next file I write I will.
Frank
It will be a right pain if you have to learn Verilog but I guess needs must. I think Varilog is similar to C.
I wonder what those converters are like, would you end up with the equivalent of a modern user manual, the gist of it being there but it not being quite right.
I am glad that I decided to go with VHDL instead of Verilog, as I get know VHLD the more I like it, it's a really nice language to use.
When I started I was getting mixed up particularly between SLV's and integer's, so I started again from scratch this time using solely std_logic and SLV's. Writing in this way is long winded but it saved an untold amount of errors. When I got a better feel for the language I introduced integer's which made the files much easier to read. I still haven't used boolean but the next file I write I will.
Frank