15-03-2017, 10:05 AM
(This post was last modified: 15-03-2017, 10:07 AM by ppppenguin.)

No need to be synchronous at all. Obviously if you have only line stores then the fields have to be coincident but with framestores the input and output can be completely async. My own experimental converter is based on a XC2S200 (now obsolete Spartan 2 series) where I have some boards left over from a professional project I did for a client. There's some SDRAM on the board which I use to make a framestore. This is a little bit complicated but the result is that video can be written to the SDRAM at the same time as 4 separate video streams can be read. This gives me up to 4 line interpolation if I wish. It's usual to do interpolation upstram of the memory for down conversion - with linestores it's essential - but since I've got framestores with full random access it's easier for me to interpolate downstream.

I've attached the central timing module from my design. Mainly to show how I used a DTO to make the 405 output clock. I took the 54MHz clock from an oscillator on the board, mutliplied up to 108MHz using the clock processing available on the Xilinx. Then used a DTO to get the required output frequency. The important bit starts at line 96. For convenience I make a 405 clock that's 4x the sample rate. This allows me to economise on logic by using 1 mutliplier to do an entire 4 line interpolator.

The observant among you will note that the 405 clock will not have equal intervals between rising edges. There is a maximum deviation from nominal of about 9ns (1/108MHz). Subjectively this doesn't show on pictures. That's why I multiplied up to 108MHz rather than only to 54MHz.

Another minor point with a DTO is that the output can never be more than half the input frequency. It is possible to get round this but it's ugly.

I've attached the central timing module from my design. Mainly to show how I used a DTO to make the 405 output clock. I took the 54MHz clock from an oscillator on the board, mutliplied up to 108MHz using the clock processing available on the Xilinx. Then used a DTO to get the required output frequency. The important bit starts at line 96. For convenience I make a 405 clock that's 4x the sample rate. This allows me to economise on logic by using 1 mutliplier to do an entire 4 line interpolator.

The observant among you will note that the 405 clock will not have equal intervals between rising edges. There is a maximum deviation from nominal of about 9ns (1/108MHz). Subjectively this doesn't show on pictures. That's why I multiplied up to 108MHz rather than only to 54MHz.

Another minor point with a DTO is that the output can never be more than half the input frequency. It is possible to get round this but it's ugly.

Jeffrey Borinsky http://www.borinsky.co.uk