24-02-2017, 09:55 AM
As a footnote I ought to say a little about my own progress through logic design.
At uni (1975-8) we did very little digital design. In my first jobs what I did was very ad hoc until a colleague showed me the principles of synchronous design. Something for which I am forever grateful. in the early 80s I used simple PLDs such as the 22V10, designing them using the ABEL language. This is easy to use and reflected how I thought about logic. The TTL and CMOS chips always had odd limitations but with ABEL I could express my thoughts about the logic rather than being distracted by the physical devices. For example if you wanted a 3 bit to 8 line decoder you would use a '138. This had a couple of enable inputs and inverted outputs. So if you wanted non-inverted outputs you needed an extra gate. In ABEL you simply wrote OUTPUT0 = (INPUT = 000) (I think, memory is dim) If you wanted the inversion you wrote OUTPUT0 = not (INPUT = 000). Similarly for other outputs that you needed.
In the early 1990s I started to use Xilinx FPGAs. Starting with the 3000 series, devices that contained just a few dozen flipflops but seemed marvellous at the time. The VHDL tools at the time were very complex and hard to use so I got the schematic entry tools which worked with Orcad. I'd been using Orcad for schematics for several years so that was no problem. I got used to the lack of flexibility; for example if I wanted a 7 bit counter I either built a macro or used the library 8 bit counter and ignored the MSB. The software was good enough to realise this and not implement unused logic.
I worked my way through several families of Xilinx parts using schematic entry (including a completely different set of software tools) and continually put off learning VHDL. Finally a friend gave me a couple of VHDL tutorials and I groped my way into it. Finally I could express myself freely in VHDL and ahve done some fairly complex designs using it. I'm about to move to Xilinx's newer Vivado tools as I'll be doing my first job with their 7 series devices.
One thing I had to get used to in VHDL was the very fussy way it handled signals. The basic std_logic is different from boolean. So I couldn't just write:
OUTPUT0 <= (INPUT = "000");
because (INPUT = "000") is by its nature boolean while OUTPUT0 would likely have been declared as std_logic. Of course there are conversions but you have to do them explicitly. Also hard to grasp at first is the many ways of defining a multi-bit signal. std_logic_vector is just a row of bits. You can also define a row of bits as unsigned, signed or integer. The handling and conversion of all this can get a bit tricky until you're used to it. In my example I assumed that INPUT was a std_logic_vector. It could have been an integer in which case I would have written:
OUTPUT0 <= (INPUT = 0);
At uni (1975-8) we did very little digital design. In my first jobs what I did was very ad hoc until a colleague showed me the principles of synchronous design. Something for which I am forever grateful. in the early 80s I used simple PLDs such as the 22V10, designing them using the ABEL language. This is easy to use and reflected how I thought about logic. The TTL and CMOS chips always had odd limitations but with ABEL I could express my thoughts about the logic rather than being distracted by the physical devices. For example if you wanted a 3 bit to 8 line decoder you would use a '138. This had a couple of enable inputs and inverted outputs. So if you wanted non-inverted outputs you needed an extra gate. In ABEL you simply wrote OUTPUT0 = (INPUT = 000) (I think, memory is dim) If you wanted the inversion you wrote OUTPUT0 = not (INPUT = 000). Similarly for other outputs that you needed.
In the early 1990s I started to use Xilinx FPGAs. Starting with the 3000 series, devices that contained just a few dozen flipflops but seemed marvellous at the time. The VHDL tools at the time were very complex and hard to use so I got the schematic entry tools which worked with Orcad. I'd been using Orcad for schematics for several years so that was no problem. I got used to the lack of flexibility; for example if I wanted a 7 bit counter I either built a macro or used the library 8 bit counter and ignored the MSB. The software was good enough to realise this and not implement unused logic.
I worked my way through several families of Xilinx parts using schematic entry (including a completely different set of software tools) and continually put off learning VHDL. Finally a friend gave me a couple of VHDL tutorials and I groped my way into it. Finally I could express myself freely in VHDL and ahve done some fairly complex designs using it. I'm about to move to Xilinx's newer Vivado tools as I'll be doing my first job with their 7 series devices.
One thing I had to get used to in VHDL was the very fussy way it handled signals. The basic std_logic is different from boolean. So I couldn't just write:
OUTPUT0 <= (INPUT = "000");
because (INPUT = "000") is by its nature boolean while OUTPUT0 would likely have been declared as std_logic. Of course there are conversions but you have to do them explicitly. Also hard to grasp at first is the many ways of defining a multi-bit signal. std_logic_vector is just a row of bits. You can also define a row of bits as unsigned, signed or integer. The handling and conversion of all this can get a bit tricky until you're used to it. In my example I assumed that INPUT was a std_logic_vector. It could have been an integer in which case I would have written:
OUTPUT0 <= (INPUT = 0);
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv