Building a Standards Converter

[`FRANK.C]

I have the project files available in a zipped folder. If anyone wants them send me a PM with your email address.

When using the files. Unzip the folder and place on drive C. Open the project in Quartus and compile it. It should compile OK with 14 warnings. These warnings are OK and can be ignored.

There are a couple of things to check before using it to program a FPGA.
First check that the Dual-purpose pins are set as I/O pins.
To do this in Quartus on the Tool bar go to 'Assignments' and then
'Device' => 'Device and pin Options' => 'Dual-purpose pins' and set both pins to 'Use as regular I/O'

Next check that the Unused pins are set to tri stated.
To do this in Quartus on the Tool bar go to 'Assignments' and then
'Device' => 'Device and pin Options' => 'Unused pins' and set to ' As input tri-stated'

After setting the pins recompile.

Before programming the output file (hedghog.sof) needs to be converted to a (.jic) file
To do this in Quartus on the Tool bar go to 'File' and select 'Convert programming files'.
In the pop up window setup as in the screen shot below.
In the example below the (.jic )file is named 'hedghog_test_01.jic' but any name can be used.

Frank

[`FRANK.C]

In case the above is not clear this may help a little

To convert a .sof file to a .jic file the following has to be set

'Programming file type'   set to 'JTAG Indirect Configuration File(.jic)'
'Configuration device'    set to 'EPCS4'
'File name'    set to whatever you want to name the (.jic) file the default name is output_file.jic
'Flash Loader'   select 'Add device' => 'Cyclone II' => 'EP2C5'
'SOF data'   select 'Add file' => C:\hedghog_project_files\output_files\hedghog.sof

Frank

[ppppenguin]

Just to make it clear, when Frank refers to"proejct files" he means the source VHDL etc files needed to program the Altera FPGA. If you can work in VHDL you can modify them as you wish to change the functionality of the Hedghog.

Releasing these files means that the Hedghog is now completely open source. All credit to Frank for making all aspects of the design freely available at no charge. That's free in both senses: Freedom to use and modify the design as you wish, and at no charge, as in "free beer".

[Jac Janssen]

Hello Frank,

Thank you!

Each time I see more of the Hedghog, my admiration for you rises even further!


The compilation (twice) and converting to .jic is complicated, but it worked first time thanks to your excellent instructions!
I programmed the Hedghog with the new .jic file, and it works as before.
I also noticed that the 3 test lines (with equalization pulses on) are still present.

Best regards,
Jac

[`FRANK.C]

Hi Jac
There should be a difference in the active video. It is right up to the equalising pulses now. The actual video might not fill the last line of a field.

If you want it to go right up to the equalising pulses it can be done by adjusting where FRAME_RESET resets V_COUNT to.  in the out_405 file. Line no. 475.
TR_CLR (time redistribution memory clear) in the in_625 file may also need to be adjusted. Line 366.

One thing that I am after spotting is line no. 400 of the out_405 needs to be changed to

if FRAME_RESET = '1' then H_COUNT <= 0; HALF_LINE <= false;

as it is one sync pulse in a frame might be skipped.

I will be releasing a new programming file for hedghog shortly it will have a few improvements.

Frank

[Jac Janssen]

Thanks Frank,

You are absolutely right of course: I just had a brief look on my Pye, but did not investigate too carefully.
Sorry about that.
The lines are indeed now missing. Thank you for that.

The coming days I'll try to find the mentioned lines. At this moment it still all is abracadabra to me...
But hopefully I'll learn something about it.
I am very much used to analog circuits, so I'll just have to widen my horizon a bit  

A, probably stupid, question (with possibly many to come...): is there somewhere in the project files or in the Quartus program a kind of (functional) block diagram available, to study how the standards converter actually works?


Jac

[ppppenguin]

If you're working in VHDL you don't get a block diagram. I don't know about the Altera tools but the Xilinx tools will generate a sort of schematic from the VHDL. It's more or less useless as it has no understanding of the level of detail you want.

One of the arts of VHDL design is dividing up the design in a sensible way. Then you can see a hierarchy that shows the functional blocks of the design in a meaningful way. It's not easy to do a really good job here. Sometimes it may not even be possible. I usually also put a lot of comments at the start of each VHDL module, saying how it relates to those above and below it in the hierarchy. But a block diagram is nice, even if you have to sketch it out by hand.

[`FRANK.C]

Hi Jac
As Jeffrey has said Qartus will generate a type of schematic but it is far too detailed and very difficult to follow unless you are very familiar with the VHDL files.
The screen shot below is a inheritance diagram generated by Doxywizard. It might give some idea how the files are connected together.
I have listed the files below and given a brief description.

The VHLD files:

hedghog    Top level  entity. This is the main file. It's port connects to the outside world (the FPGA pins)
in_625  This file contains most everything that is clocked from the 625 line clock
out_405 This file contains most everything that is clocked from the 405 line clock
i2c_com This file does the I2C communications
pattern_gen This file generates the test card and greyscale.

Entity's that are created with the' MegaWizard plug-in manager':

fifo_1ld  FIFOs used for a one line delay.
fifo_tr FIFO used for time redistribution
pll_1  PLL that generates a 216 MHz clock from the 27 MHz video clock. The 216 MHz clock is used to generate the over sampling and 405 clocks
pll_2 PLL that generates a 16 MHZ clock from the 50 MHz FBGA board clock.  this is then used to generate the Modulators  and I2C clocks.
int_mult Multipliers used in the interpolater.
output_mult Multiplier used for inserting the pedestal.
mult_os  Multipliers used in the over sampler.

keep the questions coming they are all good.

Frank

[Jac Janssen]

Thanks Frank,

This helps.

Jac

[ppppenguin]

The vision carrier is definitely 45.5MHz on Ch1. See attached screenshot from my spectrum analyser. Ch2 is correct at 51.75MHz. i haven't checked others. Sound carrier correct on both channels.

Definitely needs to be fixed. Would be a lot easier to read the settings in i2C_com.vhd if the constants were in hex, not binary. I think I've translated this correctly:

constant CH1_CF_DATA : ic2_data_array := ( X"3D00", X"B380", X"3980", X"D380");

I know some of the values are specified bitwise but looking at strings of 16 bits makes your eyes go funny. I think the newest version of VHDL allows you to put separators in a binary value 0000_0101_1011 or something like this but I don't think the version we're using allows this.

Looking at the modulator data sheet I think I'd be specifiying these constants differently altogether. For example there is a 12 bit value to specifiy the carrier frequency. I might well say something like:

constant CARRIER_FREQ_CH1 : std_logic_vector(11 downto 0) : conv_std_logic_vector(47,11);

This clearly shows the number in decimal. Then concatenate the bits and pieces to make CH1_CF_DATA etc

I haven't tried to put the bits in the correct places but you only have to get this right once.

constant CH1_CF_DATA : ic2_data_array := ( xxxx & CARRIER_FREQ_CH1 (4 downto 0) & yyy) etc etc