Building a Standards Converter

[ppppenguin]

A couple of general point about logic design.

Wherever possible make everything synchronous to clock. This avoids all sorts of trouble. It's not obvious whether the set and clear inputs of the flipflops on your schematic are synchronous or not. In the days of TTL and CMOS most parts were not ideal for good synchronous design. In PLDs and FPGAs it's the natural way of designing.

A corollary of the above is to register all signals if at all possible. Registers are essentially free in programmable logic. Again it avoids all sorts of problems, mainly to do with propagation delays.

Never put a gate in s clock signal unless you really know what you're doing and even then avoid where possible. All flipflops in PLDs and FPGAs have a clock enable input so use a single clock to all of them and control via the CE input. It's nice and easy to do this in VHDL. Even if there isn't a physical CE input the synthsis engine will produce an equivalent result using gates and feedback. Obviously in a 625 to 405 converter there will be 2 clocks, one each for input and output. If any signals have to cross a clock domain boundary then special care is needed.

In the example below I'm using a 54MHz clock for everything on the 625 side which 4x the pixel rate. Then a divide by 4 gives me clock enables at 13.5MHz.

process (CK) begin
if rising_edge(CK) then
if CE='1' then --These run with standard CE (13.5MHz)

-- Central horizontal 13 bit counter. Line length up to 4125 pixels
if HRESET then HCOUNT <= 0; -- Reset at terminal count
else HCOUNT <= HCOUNT + 1 mod 8192; -- Normal count
end if;

end if; -- CE

end if; -- CK
end process;

[`FRANK.C]

Hi Jeffery
Thanks for the tips they are appreciated, all this is new to me. I have been playing with electronics since the early 80's and its hard to believe, that in all that time I have never used a flip flop.

I have found some flip flop symbols with clock and enable inputs in the symbols library and will use them where practical.

Frank

[ppppenguin]

Look carefully at the flipflops you are using. You may find that some have synchronous set and reset inputs while others are async. Avoid the async ones unless you know exactly what you want to achieve.

The great thing about synchronous logic is that it"just works" provided hat you don't exceed the maximum clock speed as predicted by the CPLD/FPGA tools for your designs. At the clock speeds you'll be using you'd have to try very hard to run into that sort of problem.

[ppppenguin]

As a footnote I ought to say a little about my own progress through logic design.

At uni (1975-8) we did very little digital design. In my first jobs what I did was very ad hoc until a colleague showed me the principles of synchronous design. Something for which I am forever grateful. in the early 80s I used simple PLDs such as the 22V10, designing them using the ABEL language. This is easy to use and reflected how I thought about logic. The TTL and CMOS chips always had odd limitations but with ABEL I could express my thoughts about the logic rather than being distracted by the physical devices. For example if you wanted a 3 bit to 8 line decoder you would use a '138. This had a couple of enable inputs and inverted outputs. So if you wanted non-inverted outputs you needed an extra gate. In ABEL you simply wrote OUTPUT0 = (INPUT = 000) (I think, memory is dim) If you wanted the inversion you wrote OUTPUT0 = not (INPUT = 000). Similarly for other outputs that you needed.

In the early 1990s I started to use Xilinx FPGAs. Starting with the 3000 series, devices that contained just a few dozen flipflops but seemed marvellous at the time. The VHDL tools at the time were very complex and hard to use so I got the schematic entry tools which worked with Orcad. I'd been using Orcad for schematics for several years so that was no problem. I got used to the lack of flexibility; for example if I wanted a 7 bit counter I either built a macro or used the library 8 bit counter and ignored the MSB. The software was good enough to realise this and not implement unused logic.

I worked my way through several families of Xilinx parts using schematic entry (including a completely different set of software tools) and continually put off learning VHDL. Finally a friend gave me a couple of VHDL tutorials and I groped my way into it. Finally I could express myself freely in VHDL and ahve done some fairly complex designs using it. I'm about to move to Xilinx's newer Vivado tools as I'll be doing my first job with their 7 series devices.

One thing I had to get used to in VHDL was the very fussy way it handled signals. The basic std_logic is different from boolean. So I couldn't just write:

OUTPUT0 <= (INPUT = "000");

because (INPUT = "000") is by its nature boolean while OUTPUT0 would likely have been declared as std_logic. Of course there are conversions but you have to do them explicitly. Also hard to grasp at first is the many ways of defining a multi-bit signal. std_logic_vector is just a row of bits. You can also define a row of bits as unsigned, signed or integer. The handling and conversion of all this can get a bit tricky until you're used to it. In my example I assumed that INPUT was a std_logic_vector. It could have been an integer in which case I would have written:

OUTPUT0 <= (INPUT = 0);

[`FRANK.C]

In the early 1990s I started to use Xilinx FPGAs. Starting with the 3000 series, devices that contained just a few dozen flipflops

Hi Jeffery

That’s unheard of! Or at least it is to me. I always thought of FPGA's of having gazillions of devices in them. You certainly have seen some changes over a relatively short time. One thing about FPGA's that seems odd is that most of them appear to require external program memory. It would seem more convenient if they had it internally but no doubt they have a good reason for doing it that way.

I was having a look for documentation on Quartus Prime schematic entry and in particular on the symbols but haven’t found any. There is plenty of documentation on Quartus Prime but it all relates to HDL, which I guess is understandable.

I suspect the reset inputs on the flip flops are synchronous as the schematic entry appears to be designed to be pretty idiot proof, with probably, having the trade off of being restrictive compared to HDL.

Frank

[ppppenguin]

Please don't assume anything about those flipflop symbols. Read the manual to check.

you probably won't find schematic entry for current generation parts. You're expected to design with vhdl or verilog.

A few fpgas have built in boot memory. Most don't.

[`FRANK.C]

Hi Jeffery
I agree with you about not assuming but in the absence of a manual all I can do is proceed with caution.

A couple of photos of the progress so far. The photos are from a simple interpolater where the discarded line is split 50:50 between the adjacent kept lines.

The discarded line is divided by 2, by right shifting it and discarding the LSB, it and the kept line is then fed to an adder. Because each successive discarded line is on a alternate FIFO a multiplexer is used to control which line is the one divided by 2. After interpolating another adder is used to insert the sync pulses.  

Frank

[ppppenguin]

Looks good.

All the documentation for the Altera software should be available online. That's certainly true for the Xilinx software which I use.

[`FRANK.C]

Just a update as to what is happening with this project as progress is slow.
I intend to improve the interpolater from the simple 50:50 one that I am using to a proper two line one. Doing this using schematic entry seemed difficult so I have decided to try and learn some VHDL.  
I have learned a tiny bit, enough to rewrite the schematic I have in VHDL.
Just for comparison I have uploaded a file that replaces the schematic that I uploaded earlier in this tread.  

In order to have more resources to play with I have ordered a Cyclone IV EP4CE6 FPGA. It has over 6000 cells a opposed to the CPLD which has 192. Even though the FPGA has 270kbit of RAM I will be sticking to the frame stores that I have for now at least.

When I get the interpolater sorted one thing I would like to do is make the aspect ratio switchable between 4:3 and 5:4.  It would seem straightforward enough to do. The active video signal from the decoder is programmable and could be used to chop the beginning and end from each line, when in 5:4 mode.
The 405 clock would need to be reduced in frequency when on 5:4 in order to stretch the reduced number of pixels to fill the full line. To do this, I was thinking of using a AD9851 DDS module as the 405 clock source.

Frank

[Murphyv310]

Good work Frank. Way over my head though.
Funny thing is I would have thought David Boynes would have been a big contributor on the thread.