21-09-2019, 07:42 PM
Hi Jeffrey
The windowed output looks really good.
Windows are really useful for viewing a non standard number of lines. I was experimenting a while back with a converter that could convert from 625 to any number of lines between 30 and 405. A window allowed me to view the output on a 405 set regardless of the number of output lines. This was useful to observe how well the interpolater was doing at a given number of lines. A frame store is essential to do a window.
I had to park this project for a while. Before I did I made a little progress. I got it working without using the frame store.
The memory that would be normally used for time redistribution when doing 625 to 405 I have used to provide a one line buffer between the 405 output and the 625 interpolater.
This allows the 625 output to wobble around a little without running out of information.
I implemented a type of PLL for the output clock by counting the number of pixels in a frame and altering the DTO coefficient to keep the number of pixels correct.
It works quite well. Two photos below The first with the PLL disable the second with it enabled.
The PLL adjusts by different amounts dependant on how far the count is from the target.
When the PLL locks a flywheel engages and only allows small changes. If it is off target for an extended length of time the flywheel is disengaged.
For 405 input I use a Frewview box playing mp4's stored on a USB stick. A Hedghog converts the 625 to 405.
How well the 405 to 625 converter works is dependant on what recording is being viewed.
Some recordings convert perfectly with the PLL having an easy time keeping on track. Some scenes on other recordings the PLL has to work very hard with some visible effects on screen.
I had expected that the syncs from a Freeview box would be constant regardless of the recording. Maybe some rubbish is getting into the sync area of the raw video and affecting the sync separator. I have tried slicing at different levels to no effect. I will have to investigate further when I get back to the project.
I have had another thought on providing an output clock.
In post #20 looking at the scope trace of the video clock it can be seen that every forth cycle looks reasonably in phase.
Dividing by 4 should clean up one edge or dividing by 8 would clean up both. It might clean it up enough to allow it to drive the PLL in the FPGA reliably. The only trouble is that even dividing by 4 will take the frequency below the minimum clock frequency (5MHz) that the PLL will operate with.
Frank
The windowed output looks really good.
Windows are really useful for viewing a non standard number of lines. I was experimenting a while back with a converter that could convert from 625 to any number of lines between 30 and 405. A window allowed me to view the output on a 405 set regardless of the number of output lines. This was useful to observe how well the interpolater was doing at a given number of lines. A frame store is essential to do a window.
I had to park this project for a while. Before I did I made a little progress. I got it working without using the frame store.
The memory that would be normally used for time redistribution when doing 625 to 405 I have used to provide a one line buffer between the 405 output and the 625 interpolater.
This allows the 625 output to wobble around a little without running out of information.
I implemented a type of PLL for the output clock by counting the number of pixels in a frame and altering the DTO coefficient to keep the number of pixels correct.
It works quite well. Two photos below The first with the PLL disable the second with it enabled.
The PLL adjusts by different amounts dependant on how far the count is from the target.
When the PLL locks a flywheel engages and only allows small changes. If it is off target for an extended length of time the flywheel is disengaged.
For 405 input I use a Frewview box playing mp4's stored on a USB stick. A Hedghog converts the 625 to 405.
How well the 405 to 625 converter works is dependant on what recording is being viewed.
Some recordings convert perfectly with the PLL having an easy time keeping on track. Some scenes on other recordings the PLL has to work very hard with some visible effects on screen.
I had expected that the syncs from a Freeview box would be constant regardless of the recording. Maybe some rubbish is getting into the sync area of the raw video and affecting the sync separator. I have tried slicing at different levels to no effect. I will have to investigate further when I get back to the project.
I have had another thought on providing an output clock.
In post #20 looking at the scope trace of the video clock it can be seen that every forth cycle looks reasonably in phase.
Dividing by 4 should clean up one edge or dividing by 8 would clean up both. It might clean it up enough to allow it to drive the PLL in the FPGA reliably. The only trouble is that even dividing by 4 will take the frequency below the minimum clock frequency (5MHz) that the PLL will operate with.
Frank