Golborne Vintage Radio

Frank, I was looking at the 5150 data sheet again and saw something that might be useful.

See 2.20.14 YCbCr data path bypass. This should put raw ADC data on the digital output, just as I did with the SAA7118. It's better (lower jitter) to get H sync from a dedicated pin than from slicing the raw digits. This is possible because you can conenct H sync to a separate pin on the 5150. Again just as I could with the 7118.

Had another look around the stores to see if I had any more hardware for this project. Not that I'm planning to make many of these but they are useful experimental platforms. I know I've got more 5V SM PSUs somewhere but can't find them. I sold a load at Harpy and NVCF a few years ago but kept some back. Ultimately they are a standard part from RS and many others but it's still annoying when you know you've got them.

Found a few of the necessary BNC connectors, some used, some new. See picture. All doubles and not very many of them. I could do with some of the singles and triples if anyone has them lurking. Again they can probably be bought easily from somewhere as they're not exactly exotic.

I also found a few more main boards -  I now have about 8. More than enough. Plus a load more of the video I/O modules. Got more SDI I/O than I know what to do with and plenty of analogue inputs. The real bonus was 6 of the analogue outputs. A vast improvement over the 2 had I already found. Means I can afford to give my 405-625 converters both analogue and digital outputs.

Hi Jeffery
Well spotted.
I had read over that but seen "digitized S-video luminance" and discounted it. Worth jiving it a try at some stage.

I have been thinking about Hedghog II.
It has no framestore and I cant use a PLL to generate the output clock from as the video clock from the video decoder is too jittery.
But I was thinking of trying to lock the output clock by counting the number of output pixels in a full frame and keep it at a constant 864 X 405 = 349920 by adjusting the DTO coefficient.
Too many pixels reduce the coefficient, too few increase the coefficient. Better still count the oversampling clock which is pixel frequency X 4.
It might be worth a try sometime.

Frank

Your clock lock idea could work. Never tried that sort of PLL before but no reason why it shouldn't work.

I thought I had more of those BNCs. A box of a few hundred assorted new ones has just turned up. Just by looking in the right place. They include some blocks of 5 which are ideal for the job.

Maybe the 5V PSUs will turn up next next but I've got enough for now.

Hi Jeffery
You did well to find the connectors. In situations like that I usually don't find them until I have ordered more .

I tried bypass and it works I connected the output from the decoder directly to the DAC and connected a scope. Picture below.
But when in bypass mode H sync gets turned off on the separate pin and replaced by what looks like a clock.

Frank

What happens if you try register 47h bits 3 and 4 set to 01 instead of 10? In the same register what does this really do if you set it to 000 instead of the default 111? Does the sync come out somewhere else? And what about the reserved settings. If you are trying to do something a bit special it can be worth poking around the reserved values.

YCbCr output format:
000 = 8-bit 4:2:2 YCbCr with discrete sync output
001 = Reserved
010 = Reserved
011 = Reserved
100 = Reserved
101 = Reserved
110 = Reserved
111 = 8-bit ITU-R BT.656 interface with embedded sync output (default)

Are you looking at HSYNC on pin 25? Or elsewhere? Pin 26 (AVID) might be useful. HSYNC is affected by register 03h bit 2.

Hi Jeffery
I was checking pin 25 with register 03h bit 2 set to enable that pin.
I have the VHDL wrote to connect a DIP switch to register 0Dh bits (4 downto 0) so next chance I get I can whizz through all the combinations.

Frank

Hi Jeffery
Playing around with the settings has paid off .
I haven't been able to get clean syncs on bypass plus H sync on a separate pin.

What I can get is syncs that start off OK but then the rest of the sync is obliterated with a burst of some description but still should be able to use to extract odd/even.  On the plus side the embedded syncs are still there so wont need a separate H sync pin.
I will have to extract odd/even field. I will have to have a think about that as I haven't done it before but having good embedded H sync should make it easier.

The first two photos below are the output straight from the decoder showing H sync and V sync.
The last photo is the bypassed video going through the converter seen on 625 lines. The video is sitting on a pedestal the height of the 405 syncs. This can be easily be removed and adjusted to give full video range.
Sorry about poor photos I am not using my usual scope.

Frank

That burst is very odd.

You may recall that I had to adjust the gain and black level of the raw ADC output. The ADCs in the SAA7118 are 9 bit with the LSB accessible on another pin. Not sure how much difference the extra bit makes but it's certainly used by the decoder part of the chip. 8 bits wre always a touch marginal for digitising an entire composite signal. Professional users have used 10 bit SDI interconnects for many years.

In critical applications, where you want to go from (say) a 10 bit representation to an 8 bit then truncation isn't good enough. The usual method in the broadcast industry is Dynamic Rounding, develope by Quantel. This is reckoned to give better results than dither or other simple rounding methods. I admit I haven't bothered with any clever rounding in the 405 to 625 converter. There's enough noise on the input to provide ample dither.