07-04-2019, 02:02 PM
This project was prompted by the availability of cheap GPS modules from china (ebay).
The module chosen was based on the ublox NEO-7M. This is not the best module for timing but it is a lot cheaper, under £6, than dedicated ones. (It does require an active aerial, under £3.)
The NEO-7M does not any flash memory for storing the configuration data and the backup battery for the RAM does not last long.
The simplest solution is to use a microcontroller to configure the module via the serial port at power-up; once configuration is completed the micro is free to be used for other purposes e.g. as a synchronous divider.
The NEO-7M can produce a time-pulse selectable from 1Hz to 10MHz in 1Hz steps, like all(?) GPS devices this is derived from a numerically controlled oscillator (NCO) and will have jitter on its output equal to at least one cycle of the internal clock. For the NEO-7M the clock is at 48MHz and thus the minimum jitter is approximately 20nS.
There are at least two components contributing to the jitter.
Firstly if the output frequency is not a submultiple of 48MHz then cycles will be dithered to give the correct sequency. e.g. 10MHz is generated by a sequence of 10 half cycles each with a length of 2 or 3 clock periods to give a total length of 24 clock periods or 5 cycles in 24* 1/48M = 500ns.
At 1MHz there is no jitter from this cause.
Secondly the 48MHz clock (which is a simple crystal oscillator for the -7M) is not locked to the GPS and again a clock cycle must be ‘lost’ (or gained?) periodically to maintain the correct output frequency. This is the sawtooth effect, the time error builds up until a clock cycle is lost to correct the error.
For the simplest frequency reference e.g. checking the calibration of a counter the output of the module may be used directly. (see ‘Test’)
To provide a jitter free frequency reference an external oscillator must be disciplined by the GPS module, the more stable this oscillator is, the slower the correction required to hold it within the required limits. Usually a high quality ovened crystal oscillator is used with a very long control time constant giving great accuracy (~ 1 in 10^11) after a very long settling time (hours).
I built such a GPSDO several years ago but found what I really wanted was something that gave reasonable accuracy (better than 1 in 10^8) within a few minutes after power-on.
For me other desirable features were a selectable output frequency, simplicity and low cost.
When I found a micro oven crystal oscillator (10MHz) with a warm-up time of 60sec to within 1 in 10^7 of final frequency and a temperature stability if +/- 0.2ppm 0 to 60oC this project gelled.
I have used PIC processors in the past but for this project chose an AVR processor for its hardware division capabilities (the clock input can be divided by any even ratio from 2 upwards).
(The AVRs also have very low cost hardware and software for programming e.g USBasp and AVRdudess.)
As most of the program involved manipulating registers and I/O, assembly language was chosen. I used an old version of AVRstudio (4.18) as the newer versions are far too bloated for my liking.
For simplicity, cost and availability I chose the ATtiny85 (in 8 pin DIP).
In order to achieve the desired settling speed a phase lock loop with a relatively high comparison frequency was chosen.
The NEO-7M and AVR divider are easily programmable over a wide range allowing the PLL time constant to be adjusted by varying the comparison frequency.
Settling speed may be traded against smoothing of GPS short term instabilities as required.
PLL design
Since both inputs are square waves (1: M/S) an exclusive OR type phase comparator was chosen for simplicity and its mid rail output when one input is missing.
Output from GPS module is 0 - 3.3v so 4046 was used with ‘Signal in’ AC coupled.
(4046 chosen for availability in DIP (ebay), 74HC4046 or 74HCT86 directly coupled could be used)
‘Gain’ of (exOR) phase comparator (Kp) = 10V/Cycle (5v in 180o)
For 10MHz OCXO used ‘Gain’ (Ko) = 25Hz/V
Try 10kHz comparison frequency, divider ratio required (N) = 10k/10m = 1000
This gives PLL time constant (T) = N/(Ko*Kp) = 1000/(25*10) = 4 sec
Rule of thumb (Dominant Lag) - for good stability largest time constant in loop should be at least 4 times the sum of all other time constants.
Choose loop filter as single RC section with 1s time constant.
Measured OCXO control input resistance approximately 1M so choose 22k & 47uF to avoid loss of tuning range.
Add a second RC section to further attenuate 10 kHz from comparator choose 10k & 1uF.
Max OCXO error at extremes of tuning range ~ 100Hz giving 0.1Hz at phase comparator so output of filter should sweep almost full range (0-5v) at OCXO control input and thus easily acquire phase lock.
Simulation confirmed satisfactory performance.
Output divider
A range of output frequencies is provided by a second ATtiny85 again clocked from the OCXO.
It also provides a fixed 10MHz output from its clock buffer pin.
A 10 way switch is used to select frequencies of Off, 5M, 2.5M, 1M, 100k, 10k, 1k, 100, 10 or 1Hz
(Off position ensures no subharmonics on 10MHz output.)
ATtiny85 has limited number of I/O pins so resistor chain and (single) Analog Input pin was used.
Running the A/D continuously would compromise output purity so the comparator was used to generate interrupt when switch position changed.
This was achieved by the use of ten resistors in two chains arranged such that odd switch positions give voltages below the internal comparator reference (1.1v) and even positions give voltages above.
The ‘interrupt on comparator change’ function is then used to start the A/D only when required.
(The switch I used was MBB so the wiper was always connected. A stop was required between positions 1 and 10 to avoid shorting the supply.)
Adding a USB-TTL serial module (ebay again!) gives the ability to monitor the NMEA data from the GPS module (once per second), when the USB port is not in use the GPS module is reconfigured to suppress the output of NMEA messages. (I’m not sure if this avoids 1Hz spurii but it makes me feel better if nothing else!)
(There is a slight penalty in that the divider output stops for approximately 2.5mS at the changeover but this does not cause much of a glitch. The delay is arranged to be an integer number of cycles at the comparison frequency.)
Power supply
A stable power supply is required and for lowest noise a linear supply is best, however low power dissipation is desirable to minimise heat rise within the equipment, ventilation would allow drafts to have more of an effect.
I chose an external power ‘brick’ and an internal switch-mode regulator with a lot of filtering (and a crowbar to protect the OCXO in case of regulator failure).
The zip file attached contains compiled and source code files for the ATTiny85s, fuse settings are in the source code headers.
'Test' is a simple circuit using the time pulse output of the NEO-7M to give a selection of preset frequencies from 1Hz to 10MHz (with jitter!).
Jim
The module chosen was based on the ublox NEO-7M. This is not the best module for timing but it is a lot cheaper, under £6, than dedicated ones. (It does require an active aerial, under £3.)
The NEO-7M does not any flash memory for storing the configuration data and the backup battery for the RAM does not last long.
The simplest solution is to use a microcontroller to configure the module via the serial port at power-up; once configuration is completed the micro is free to be used for other purposes e.g. as a synchronous divider.
The NEO-7M can produce a time-pulse selectable from 1Hz to 10MHz in 1Hz steps, like all(?) GPS devices this is derived from a numerically controlled oscillator (NCO) and will have jitter on its output equal to at least one cycle of the internal clock. For the NEO-7M the clock is at 48MHz and thus the minimum jitter is approximately 20nS.
There are at least two components contributing to the jitter.
Firstly if the output frequency is not a submultiple of 48MHz then cycles will be dithered to give the correct sequency. e.g. 10MHz is generated by a sequence of 10 half cycles each with a length of 2 or 3 clock periods to give a total length of 24 clock periods or 5 cycles in 24* 1/48M = 500ns.
At 1MHz there is no jitter from this cause.
Secondly the 48MHz clock (which is a simple crystal oscillator for the -7M) is not locked to the GPS and again a clock cycle must be ‘lost’ (or gained?) periodically to maintain the correct output frequency. This is the sawtooth effect, the time error builds up until a clock cycle is lost to correct the error.
For the simplest frequency reference e.g. checking the calibration of a counter the output of the module may be used directly. (see ‘Test’)
To provide a jitter free frequency reference an external oscillator must be disciplined by the GPS module, the more stable this oscillator is, the slower the correction required to hold it within the required limits. Usually a high quality ovened crystal oscillator is used with a very long control time constant giving great accuracy (~ 1 in 10^11) after a very long settling time (hours).
I built such a GPSDO several years ago but found what I really wanted was something that gave reasonable accuracy (better than 1 in 10^8) within a few minutes after power-on.
For me other desirable features were a selectable output frequency, simplicity and low cost.
When I found a micro oven crystal oscillator (10MHz) with a warm-up time of 60sec to within 1 in 10^7 of final frequency and a temperature stability if +/- 0.2ppm 0 to 60oC this project gelled.
I have used PIC processors in the past but for this project chose an AVR processor for its hardware division capabilities (the clock input can be divided by any even ratio from 2 upwards).
(The AVRs also have very low cost hardware and software for programming e.g USBasp and AVRdudess.)
As most of the program involved manipulating registers and I/O, assembly language was chosen. I used an old version of AVRstudio (4.18) as the newer versions are far too bloated for my liking.
For simplicity, cost and availability I chose the ATtiny85 (in 8 pin DIP).
In order to achieve the desired settling speed a phase lock loop with a relatively high comparison frequency was chosen.
The NEO-7M and AVR divider are easily programmable over a wide range allowing the PLL time constant to be adjusted by varying the comparison frequency.
Settling speed may be traded against smoothing of GPS short term instabilities as required.
PLL design
Since both inputs are square waves (1: M/S) an exclusive OR type phase comparator was chosen for simplicity and its mid rail output when one input is missing.
Output from GPS module is 0 - 3.3v so 4046 was used with ‘Signal in’ AC coupled.
(4046 chosen for availability in DIP (ebay), 74HC4046 or 74HCT86 directly coupled could be used)
‘Gain’ of (exOR) phase comparator (Kp) = 10V/Cycle (5v in 180o)
For 10MHz OCXO used ‘Gain’ (Ko) = 25Hz/V
Try 10kHz comparison frequency, divider ratio required (N) = 10k/10m = 1000
This gives PLL time constant (T) = N/(Ko*Kp) = 1000/(25*10) = 4 sec
Rule of thumb (Dominant Lag) - for good stability largest time constant in loop should be at least 4 times the sum of all other time constants.
Choose loop filter as single RC section with 1s time constant.
Measured OCXO control input resistance approximately 1M so choose 22k & 47uF to avoid loss of tuning range.
Add a second RC section to further attenuate 10 kHz from comparator choose 10k & 1uF.
Max OCXO error at extremes of tuning range ~ 100Hz giving 0.1Hz at phase comparator so output of filter should sweep almost full range (0-5v) at OCXO control input and thus easily acquire phase lock.
Simulation confirmed satisfactory performance.
Output divider
A range of output frequencies is provided by a second ATtiny85 again clocked from the OCXO.
It also provides a fixed 10MHz output from its clock buffer pin.
A 10 way switch is used to select frequencies of Off, 5M, 2.5M, 1M, 100k, 10k, 1k, 100, 10 or 1Hz
(Off position ensures no subharmonics on 10MHz output.)
ATtiny85 has limited number of I/O pins so resistor chain and (single) Analog Input pin was used.
Running the A/D continuously would compromise output purity so the comparator was used to generate interrupt when switch position changed.
This was achieved by the use of ten resistors in two chains arranged such that odd switch positions give voltages below the internal comparator reference (1.1v) and even positions give voltages above.
The ‘interrupt on comparator change’ function is then used to start the A/D only when required.
(The switch I used was MBB so the wiper was always connected. A stop was required between positions 1 and 10 to avoid shorting the supply.)
Adding a USB-TTL serial module (ebay again!) gives the ability to monitor the NMEA data from the GPS module (once per second), when the USB port is not in use the GPS module is reconfigured to suppress the output of NMEA messages. (I’m not sure if this avoids 1Hz spurii but it makes me feel better if nothing else!)
(There is a slight penalty in that the divider output stops for approximately 2.5mS at the changeover but this does not cause much of a glitch. The delay is arranged to be an integer number of cycles at the comparison frequency.)
Power supply
A stable power supply is required and for lowest noise a linear supply is best, however low power dissipation is desirable to minimise heat rise within the equipment, ventilation would allow drafts to have more of an effect.
I chose an external power ‘brick’ and an internal switch-mode regulator with a lot of filtering (and a crowbar to protect the OCXO in case of regulator failure).
The zip file attached contains compiled and source code files for the ATTiny85s, fuse settings are in the source code headers.
'Test' is a simple circuit using the time pulse output of the NEO-7M to give a selection of preset frequencies from 1Hz to 10MHz (with jitter!).
Jim