Golborne Vintage Radio

Thanks Jeffrey, that's a great tip I didn't think of doing arithmetic in declarations.

(05-02-2019, 09:02 PM)ppppenguin Wrote: [ -> ]That number 702 looks rather familiar

It certainly is I don't think I will ever forget it

Frank

You can declare 702 as a constant if you like and do a bit more arithmetic with symbols rather than numbers

When you're doing mutliple switchable output standards or aspect ratios you're going to end up with CASE statements to select all the parameters. A CASE statement can take an integer or SLV as its argument, integer usually looking better.  You can set up some constants to make it look better still.

constant ASPECT4x3 := 0;
constant ASPECT5x4:= 1;
etc

Thent he CASE statement reads like this:

case OUTPUTASPECT is
when ASPECT4x3
X1 <= constant1
X2<= constant2
etc
when ASPECT5x4
X1 <= constant5
X2<= constant6
etc
when others
......
end case;

Here's an example of my own code showing mutliple cases in a single when (using vertical bar as separator) and compile time arithemtic which generates no logic. HMAXFIX is a fiddle factor I defined as a constant so I could use sensible looking numbers.

Hi Jeffrey
I have not seen a vertical bar used as a separator before.
I assume in this case it is the equivalent of logical OR .

Frank

It is indeed, or alternatively a way of writing a list.

when S1080_60i | S1080_30p | S1080_60p => HMAX_VALUE <= 2200 - HMAXFIX;

could equally be written as:

when S1080_60i => HMAX_VALUE <= 2200 - HMAXFIX;
when S1080_30p => HMAX_VALUE <= 2200 - HMAXFIX;
when S1080_60p => HMAX_VALUE <= 2200 - HMAXFIX;

Purely a matter of style. I think it only works if the argument of the CASE is an integer though I could be wrong. What definitely only works with an integer is saying:

when 1 to 3 => X<=Y;

Saves writing:
when 1 => X<=Y;
when 2 => X<=Y;
when 3 => X<=Y;

It never hurts to remind that you should always put a "when else" clause in a CASE statement. Even if you know for certain that you've enumerated all the possible cases it doesn't hurt. I think the Xilinx tools require it.

Another VHDL reminder:

CASE evaluates all possible values of its argument to give a unique answer. IF/THEN/ELSE is different. The logic is evaluated in the order the lines are written.

So (J, K are boolean):

if J then Q <= '1';
elsif K then Q <= '0';
else Q <= Q; -- not essential but a useful aid to memory
end if;

is different to:

if K then Q <= '0';
elsif J then Q <= '1';
else Q <= Q; -- not essential but a useful aid to memory
end if;

They look similar but if J and K are BOTH true the 2 versions will give different answers. This may or may not matter but you need to be aware.

Hi Jeffrey
Thanks for the tips they have given me some ideas to try out on the next file that I am at which is the in_625 file.

Frank

The in_625 file is attached below. Most everything on the 625 line side of the converter is in this file. I have tried to make it easy to change to a different output standard.
Like the out_405 file there is a set of constants for each set of aspect ratios.
There are only 5 constants for each aspect ratio and only these needs to be changed to change this file to another standard.

The first is (LINES_PER_FRAME) the number of  lines in the standard been converted to.

The next two (AV_START and AV_STOP) are only needed for aspect ratio conversion and for normal operation just copy the values that are in the 4:3 => 4:3 set.

The next one (NUM_OF_INT_COEF) is the number of interpolater coefficients used. for a start I would set this value to 32. Later it can be changed to the correct amount.

The number of interpolater coefficients needed for a given number of output lines can be got by:
((32/625) X number of output lines)  and round the result up to the nearest integer.
For 405 lines:
(32/625) X 405 = 20.736 rounded up =21 coefficients.

If too many coefficients are used you get a poorly interpolated picture. If too few you get horizontal lines on the picture.
A photo below shows he horizontal lines when I drop the coefficients for 405 lines from 21 to 20.

The next is (COEF_2_LINE_CD) the array that holds the interpolater coefficients. For a start I would set all the values in this array to 127. There are 32 values in the array. This gives a poorly interpolated picture. See photo below.
When the rest of the converter is up and running and the number of coefficients are known. The values can be calculated and inserted in the array.

An example below of what I would suggest to start off with if doing 567 lines. In this case selecting 16:9 => 5:4 on Hedghog would select 567 lines instead.

Frank

Hi Frank,

All critical parts arrived and I started building the Hedghog. The TVP5150 was quite difficult because of the very small size pins, and I am not the youngest anymore.
I made some interconnections on the board because the switches have not arrived yet and used some provisional RCA connectors (right ones also not here yet).
And your brilliant design works!

Very much looking forward to 567 line operation!

Thanks again Frank for all the effort you put into this design and making it available to us all!
Jac

Looks like development is going nicely. I had a very quick look at some of the VHDL. This line could be a liability:


The clock speed is pretty low so it should work but it's a potential trouble spot in getting the design to meet its timing specs. Unless I had a very good reason not to I would always pipeline this sort of adder:


PARTIAL_SUM1 <= VIDEO_MULT_A + VIDEO_MULT_B;
PARTIAL_SUM2 <= VIDEO_MULT_C + VIDEO_MULT_D;
PARTIAL_SUM3 <= VIDEO_MULT_E + VIDEO_MULT_F;

VIDEO_SUMMED <= PARTIAL_SUM1 + PARTIAL_SUM2 + PARTIAL_SUM3;

Other signals may need to be pipelined to match this extra delay. The extra registers in the adder are a free resource as they are part of the logic cell and not being used.

If it's got to go really fast then the final sum could be split into 2 stages but that's normally for speeds much higher than used in Hedghog.

Hi Jac
Well done on getting it working, great result.
I too find the video decoder difficult, but doable.

The Hedghog project folder on my computer is fairly large at 12.5 MB in size.
I am putting together a folder of files for the project that will be only a fraction of this and so easier to distribute.  In this folder the project will not have been compiled. As after compilation the size of the project grows considerably.
When I have it ready I will post here.

Hi Jeffrey
Thanks for taking a look at the VHDL.  I will change that as per your recommendation. As the output of the adder eventually ends up been written to the time redistribution memory I just need to adjust its write enable to compensate for the added delay.
Another thing I probably should do is to pipe line the over sampler multipliers. I had meant to do it but it left my mind.

Frank

Thanks Frank,

I must admit that I was very relieved that the converter worked straight away.
I am now looking at the 405 line RF signal on several sets - at the moment at my Pye D16T.
The difference between the 3 interpolation modes is much larger than I expected it to be.
The possibility to include the pedestal is appreciated!

Looking forward to the files.
Hopefully I can understand a least a tiny bit of it...

Jac