Wonderful job and so professional looking.
Your in the wrong job Frank.
Have a few beers and enjoy St Patrick's day.
And for Frank's next project........
How about 405 to 625 conversion. This is very rarely needed now, unless a 405 line quadruplex tape turns up. Or possibly somebody has some unusual 405 material recorded on VHS etc. The main issue is that you can't use a decoder chip as the front end. I have some ideas for circuits, they're not too complex, but there are various problems to be solved.
Hi Jeffrey
That would be the 1 million pound question.
I was actually thinking of 405 to 625 but the only source of 405 I have is nice and stable from a converter. A good 405 to 625 converter would need to cope with less stable sources like VCR's. The front end would be interesting especially coping with less stable sources.
Hi Trevor
These China PCB's makes a great job of projects. Without them it would be difficult to do a project like this one as some of the tracks are just 0.2mm wide.
We were at the local parade in Ballintubber today. A clip of it was shown this evening on RTE news. Despite been well layered up we got frozen but we're off to the local later to thaw out.
Frank
The 2 main questions with a 405>625 converter are coping with imperfect sources and input filtering. If the input sampling is at around 9MHz the conversion to 625 is simple but you need a very good input filter to avoid aliasing. Alternatively you can oversample (2x or 4x) which gives a simple input filter but needs a decimating filter in the FPGA. I've designed a precision upsampling filter which uses a LOT of multipliers (161 taps, 23 multipliers) but we don't need that level of performance. There's a tradeoff between complexity and performance. I have no instinctive feel for where the sweet spot might lie. Once you have the filter coefficients then the Xilinx Coregen tools will implement the filter without difficulty.
Another approach is conceptually very simple. Keep the oversampled signal throughout the converter. Accept the increased processsing speeds and memory usage. The output is then nicely oversampled too, making the post-DAC filter very easy.
The input arrangements would normally be done by phaselocking a clock to the incoming syncs. An alternative approach would be to used a fixed sampling clock, find the sync edges and resample in digits. I know this is done in the Techwell decoder chips and works well. I don't know how complex the correlation and resampling logic will be. the correlator finds the sync edges. The resampler interpolates the input samples on to an orthogonal grid.
Lovely project and very professionally finished (I presume you are "in the industry").
It's been really interesting to follow the progress - are you going to produce any more?
It is a wonderful project Nick and Frank should be well credited for his hard work and dedication.
Perhaps Frank will come and tell us about his daytime job....... I think you might be surprised.
Hi Jeffrey
Lots of food for thought there. I would appear that digital filters are resource hungry, I had a brief play with a FIR filter sometime ago the amount of resources it used was enormous.
Hi Nick
I am not "in the industry", for the last 25 or so years I have been repairing domestic appliances but I have been dabbling in electronics since primary school. An issue of Everyday Electronics in 1980 was my first introduction to electronics, it had a photo of a 5 volt power supply on it's cover.
I got 10 PCB's made, I have built a few myself. If anyone would like to have a go at building one I have a couple of PCB's leftover and possibly programed FPGA boards to go with them. After that I will make a copy of the .jic FPGA programing file, PCB garber file, component list etc available if anyone wishes to build one.
Frank
If the FPGA has plenty of mutliplier blocks then FIRs can be implemented very easily. Tighter response specification means more taps. Higher clock frequency means that each multiplier can be used for more than 1 tap. Symmetrical filters (most of the ones we're likely to need) halve the number of multipliers.
For the Xilinx tools, the automatic implementations are effciient. Just give the coefft set and a few other parameters and you get a good design. I would hope that Altera has an equivalent tool. Getting the coeffts is another matter. There are various tools using Remez Exchange (Parks-McClellan ) algorithms to optimise the coeffts. These tools tend to be expensive or very limited. Exploring the trade-offs between passband, transition band and stopband responses can be fascinating or frustrating. For example if you want a passband flatness of 1dB how many taps will it save compared to 0.5dB. I've no idea without trying it.
Frank has had to climb a very steep hill to get the results he's achieved. I'm pleased to have given him a hand on occasiona but he's done the hard work and should take the credit.
Frank has very kindly sent me a Hedghog (it's spelled without a 2nd e) 405 line converter which arrived this morning. I've taken a look at the video output. The waveform looks good, with well shaped sync edges. Multiburst input gives the same sort of slightly messy looking result as an Aurora. In other words the higher frequency bursts look mucky on a scope but fine on a picture monitor.
The internal test card is useful but the thin horizontal lines seem to have severe interlace flicker. It may be just my eyeballs so I ought to strobe them out on a waveform monitor before passing judgement. It's possible that they are present on only 1 of the interlaced pair of fields.
Hi Jeffrey
I was using an Altera tool to build the FIR filter, it was a while ago so cant remember the details but I had to reduce the number of taps to get it to fit on the FPGA, at that time there was approximate 50% of the resources free.
I think that I may have been overambitious with the cutoff frequency
. At the time I didn't spend much time on it as it was just something that I was trying out as opposed to wanting to do it seriously.
Frank