Got channel 13 sorted. I was using a X2 prescaler only for channel 13.
X4, X8, or X16 for all the other channels. There was enough headroom to use X4 prescaler for channel 13 and doing so cured the fault.
I don't know why the X2 prescaler was causing the problem maybe the sound channel was a tad too low in frequency for the X2 to handle.
Frank
I have been playing around wit the oversampler on the output of the converter. I increased it from twice pixel rate to four times pixel rate, first linearly and then I used a couple of multipliers to give it a more sinusoid shape. I thought it was interesting to watch the over and under shots produced by the low pass filter in the video amp for each of the different types of oversampling.
Pictured below is first no oversampling, twice pixel rate oversampling, four times pixel rate oversampling liner and the final one is of four times pixel rate oversampling using the multipliers.
The scope is set to 0.1V/div. 0.2uS/div.
It is interesting to see there is not a big difference between twice pixel rate and four tines pixel rate linear.
Frank
I have been finalizing a few things. The 4:3 active line I have set to 80.25 uS. When 5:4 was been used I believe the active line was longer at around 85% of the total line length, therefore I have set the 5:4 active line to 83.75 uS.
Pictures below of a TV24 with the width reduced, the first one is 4:3 and the second is 5:4. Controls have not been adjusted between photos.
The extra active line can be clearly be seen in the second picture, predominantly on the left hand side.
The third and fourth photos is of the line blanking periods.
Frank
Yet another demonstration of the power and versatility of progrmmable logic.
I do my wrk in VHDL, the alternative hardware description language is Verilog. Annoyingly I may have to learn at least a bit of it as all the examples and IP supplied for the evaluation kit I'm using is in Verilog. The Xilinx tools can work with mixed VHDL/Verilog but I'll need to work out how you include Verilog modules in a VHDL project. I've seen free online VHDL<>Verilog translation tools but have no idea how good they are.
Hi Jeffrey
It will be a right pain if you have to learn Verilog but I guess needs must. I think Varilog is similar to C.
I wonder what those converters are like, would you end up with the equivalent of a modern user manual, the gist of it being there but it not being quite right.
I am glad that I decided to go with VHDL instead of Verilog, as I get know VHLD the more I like it, it's a really nice language to use.
When I started I was getting mixed up particularly between SLV's and integer's, so I started again from scratch this time using solely std_logic and SLV's. Writing in this way is long winded but it saved an untold amount of errors. When I got a better feel for the language I introduced integer's which made the files much easier to read. I still haven't used boolean but the next file I write I will.
Frank
Code translators work in two ways: either they essentially transliterate statements or they are a cross-compiler where the target, instead of being a processor, is another language.
The former typically generates working but very sub-optimal code often requiring significant manual editing; the latter is far far harder to achieve but generates much better quality code requiring little or no manual tuning.
Frank, boolean type is almost essential in VHDL. Whenever you say something like B <= (S = X"25"); then B is boolean. Conversion from SL to boolean is trivial:
B <= (SL = '1');
From boolean to SL is a bit clumsy unless you use a function:
Function to_std_logic(X: in Boolean) return std_logic is
variable ret : std_logic;
begin
if x then ret := '1'; else ret := '0'; end if;
return ret;
end to_std_logic;
This can be included in each module or put in a package or library.
You then say:
SL <= to_std_logic(boolean);
Hi.
I've now got a headache!!!!!!!!!!!!
Frank & Jeffrey, I'm afraid this is all over the top of my head but I will say that I am impressed with the work done and the end results, fantastic commitment.
Now I am aware of the many hours spent on the project, you'd certainly never get them back but if you made up another then all the development work is done so surely it would be a much quicker build.
So in reality what has it cost you in monetary terms aside the time?
Nick, I've looked at some comparisons between VHDL and Verilog. Verilog is definitely the simpler of the 2 languages. It has fewer types of signals, weaker typing than VHDL and a smaller range of constructs. I think it does have some better basic logic operations but nothing that can't be done in VHDL with a bit more complexity. Provided the code is intended for synthesis (as against simulation) it looks like Verilog to VHDL translation should be more or less 1 to 1 conversion, maintaining the structure of the design. VHDL to Verilog may be harder, as Verilog has no equivalent for constructs such as GENERATE which makes it easy to instantiate mutliple instances of a block of logic. Also Verilog appears not to have PACKAGES and LIBRARIES which can make it easier to re-use code across a design.
I think Verilog has extensions to increase its capabilities and some of these can go beyond what can be easily done in VHDL.
May well be a territorial thing. I think that VHDL is more common in Europe while Verilog is more widely used in the US.
(10-02-2018, 08:01 AM)ppppenguin Wrote: [ -> ]Frank, boolean type is almost essential in VHDL. Whenever you say something like B <= (S = X"25"); then B is boolean.
Hi Jeffery
For something like that I would currently write
if S = x"25" then B <= '1' else B <= '0';
I do this without even thinking, its the microcontroller programing creeping in.
Writing it proper using Boolean is much clearer and easier to read back.
As a beginner knowing where it is best to use Integer's, Boolean etc. was the difficult part but even with the limited experience that I have now it has become clearer. It's only as I learn and try to write VHDL that realize how elegant your files are.
The first microcontroller program I wrote functioned well but when I came back and looked at it a year later I cringed and immediately rewrote it as it was so badly written. I fear in a the future I will do the same with the VHDL files I have now.
Hi Trevor.
I started this project back in November 2016 and it has taken up all my spare time until now. I expect if I toted up all I have spent on it I could easily buy at least one if not two Aurora's but I am doing it for the challenge and also to learn although the more I learn the more I realize how little I know.
As for how much the parts for one would cost. I am putting together a parts list and I will post it here when complete but I would guesstimate between 80 and 100 euro. It looks small but there is still quite a number of components in it.
I would have liked to have got rid of the Development board and have everything on the one PCB but I couldn't justify doing that. The components on the Development Board would cost about 3 times the cost of the Development Board also I would need either larger PCB or a 4 layer PCB.
Frank