Golborne Vintage Radio

Just remembered that I didn't fit LED series resistors when I wired the panel. With 3.3V across the LEDs from the PLD outputs it will probably work but the PLD will be working hard and the LEDs will be rather bright, possibly enough to shorten their lives. I'll fit the resistors today, 1 for each row in the common cathode connection. Since the PLD module uses 191R (why the odd E96 value? Did they have a few 1000 surplus?) in series with directly driven LEDs I'll use 47R for 4:1 multiplexed LEDs.

The first attempt at the VHDL compiles OK. I've made no attempt to be economic with device resorurces as the PLD has vastly more than I will ever need. So I've gone for simple code that's easily understood. The FOR loops are not like loops in BASIC or other procedural language. What they do is save me typing out N of lines of VHDL when describing a M to N decoder. In this case a 4 bit binary to 10 or 16 wire decoder.

The VHDL file is renamed as a TXT file to allow it to be attached

When the documentation and reality disagree, reality is usually correct

The PLD modules arrived today. The box was so light I wondered if it had anything in it all. It was dispatched last Thursday from Estonia so no complaints about delivery.

The PLD comes pre-programmed with a test build that works the LEDs and buttons. I hooked up power and the Xilinx programming probe, whacked in my own JEDEC file and saw some activity on the pins. Very slow activity. A simple brain fade meant I was running eveything about 1000 times slower than I intended. Easily fixed by changing the divider down from 25MHz to my main clock. I decided that about 25kHz was right for my main clock that runs button scan, LED scan and router controls. So I divide the onboard 25MHz osc by 1024. Here's the 10 bit counter.

process (CK25MHz) begin

    if rising_edge(CK25MHz) then   
        CK25MHZ_DIVIDER <= CK25MHZ_DIVIDER + 1;
    end if; -- CK25MHz
end process;

-- Assign main internal clock
CK <= CK25MHZ_DIVIDER(9);

Plug in the panel I wired yesterday and there are signs of life but it's all a bit gaga. Probe aorund the IO pins and it's definitely gaga. In a Xilinx design the pin allocations and properties are specified in a UCF file. It can be done in the VHDL but it's easier to have it in the UCF (The latest Xilinx tools have replaced the UCF with something else but that's not a problem here)

Example of an entry in the UCF, saying that bit 0 of the LED_COLUMN signal is assigned to pin A12 of the device. The # is the comment delimiter and the comment tells me it's connected to pin 3 of ribbon cable A.
NET "LED_COLUMN<0>"       LOC = "A12"; # RIBBON_A<3>

The makers supply an example UCF and you would reasonably assume that device pin A12 is connected to their J3 pin 0.
net "io_j3<0>" loc = "A12" ;

J3 is one of the rows of IO pins and I'll forgive that what they call "0" is actually pin 2. So far so good. Except that my signals were all over the place. Their example UCF is all wrong. Comparing it against the supplied schematic then one or the other is very definitely riddled with errors. For now I'll assume the schematic is correct as it was done on a CAD system and it's a fair guess that they extracted a netlist from it to do the PCB layout. Hence the PCB and schematic stand a good chance of agreement. But you usually end up doing the UCF by hand, one of the less interesting jobs in the design process.

So I'll redo the UCF in accordance with the schematic and see if the signals appear in the right places. If they don't it will be a right royal PITA because the Xilinx is a BGA device and you can't see where the tracks go underneath it.

Got the pinout and a minor logic error straightened out. All the buttons work and their respective LEDs light up. Except one LED which seems to be on all the time. Lots of head scratching. It was mounted backwards. These switches are supplied with the LEDs fitted but it's possible to extract them and put them in backwards. So either the switch has always been wrong or some joker at Michael Cox Electronics (these control panels are ex Cox) took the LED out and reversed it to fool some poor test engineer.

Need to sort out the standby input and the testcard/offair switch for when it's in standby.

Also need to check the feed to the router though I haven't yet made the adaptor cable to connect the router to the controller.

The logic for the standby and testcard works OK. Need to dig out a 5V wallwart and wire up a couple of resistors to the power connector to interface it to the PLD. The panel will then be complete except for tidying up the mounting of the PLD module and dressing the ribbon cables.

LED brightness is a bit variable but can't really do anything about it. It's just that the LED forward voltage is too great a fraction of the 3V3 supply on the PLD board. Shorting out the 47R resistors brightens the LEDs but makes the variability worse so I'll just leave well alone.

Need to wire up the ribbon cable interface to the video router and see if the whole thing works. The waveforms going to the routers certainly look OK on the scope.

Also a short D15 to D15 cable to link the controls through to the audio router. Don't think I have any ribbon cable crimp D15 plugs so I'll have to do it the old fashioned way with multicore cable.

Good progress, and it will be very smart when you have finished.

Testing the video router with the control panel. I tried all inputs and outputs. All works as expected.

Need to tidy up the panel, notably find a good way to support the PLD board.

Then make the D15-D15 cable to link the audio router and that shoul dbe job done.

I might well change the tants around the voltage regs before one decides to let go. The tants in the video circuitry ought to be safe as they're not directly exposed to the power rails.

Tants changed, D15 cable assembled. Lids on for a soak test. It all works. Audio and video.

To be done:

Find a 5V wallwart
Mechanically mount the PLD board
Labelling. I'll probably just print up some card and cut it into strips.

Barely lukewarm after and hour or so.

Excellent work, Jeffrey.    Looks really good and so much better than the relay idea!

Brian, thank you.

Installation provisionally scheduled for Saturday 27th Feb.